JNScore Single
Chip Specification
JNScore
- the most advanced and complete digital GPS/GLONASS
chip for general use.
JNScore is a
complete digital chip that includes over a dozen system blocks.
The 50-Channel GPS/GLONASS/WAAS module incorporates the latest
technology, including the In-Band Interference Suppression feature. It is ideal for standalone
hand-held receivers as well applications involving larger
systems. The dual processor characteristic of JNScore allows
independent operation of different applications. For example, one
processor can be dedicated to GPS/GLONASS tracking and position
computation while the other processor is deployed for user
interfaces like map displays. The big number of flexible GPS
channels and chip's structure give possibility to use it in
various GPS application, like reliable GPS/GLONASS/WAAS
navigation, multi-antenna attitude receiver, GPS receiver with
radio communication channels. It makes possible to underuse civil
signal from all-in-view GPS satellites on the second and third
GPS frequencies, that will be available in next few years. From
the other side, the advanced power-saving technique implemented
in chip and flexibility in reference oscillator and sampling
frequency selection allow to use it in power-sensitive
applications.
- 0.18u 1.8-Volt low power
process.
- Operating conditions:
- Junction
temperature (oC, min-max): 0-125;
- Core supply voltage
(V, min-typ-max): 1.62-1.8-1.98;
- I/O Supply voltage
(V, min-typ-max): 3.0-3.3-3.6.
- Die size is 120 square mm.
- More than 512 kB Embedded
SRAM memory.
- Analog macrocells:
- PLL for CPU system
clock synthesis (frequency can be changed by
program);
- Three 8-bit DACs
for Video Adapter RGB output;
- Package: BGA456, size
35x35x2.33mm.
- Direct spread spectrum
(DSS) code (M-sequence or Gold code) generator with
generic polynom length up to 28. Cover next cases: GPS
C/A code including WAAS and EGNOS, GLONASS C/A or P code.
Flexible DSS code choice.
- Each channel can be used as
communication channel to receive SS signals. It designed
to make possible to track signal and receive differencial
corrections from DGPS system like Omnistar.
- Two or three level input
signal, five-level carrier reference.
- Each channel can be
connected independently to 5-10 independed signal inputs.
- Sampling rate from 5 to 40
MHz.
- Carrier and code multipath
mitigation.
- Accelerated acquisition and
lock.
- Asynchronous PLL/DLL
control to decrease latency of loop control.
- Improved anti-jamming
modules having faster reaction on interference and less
signal distrotion.
- 40 MHz maximum clock cycle.
- Integer arithmetic unit.
- FPU supports ANSI/IEEE Std
754/1985 single and double floating point processing,
including division.
- Fast integer multiply to
accelerate DSP tasks.
- Debugging capabilities:
- Tunable breakpoint
registers (one per processor), can generate
interrupt on execution of instruction with given
address.
- Tunable watchpoint
registers (one per processor), can generate
interrupt on any preselected condition from:
- Read access
to any given address;
- Write
access to any given address;
- Read or
write accesses to any given address.
- On-chip boot loader
ROM provides the capability to load and debug
either CPU independently, from either SPI or
RS-232C port.
- Possibility to
monitor operations on internal data bus on
external outputs.
- Flexible boot loader
algorithm.
- Associative Instruction
Buffer of 4kB size (only Master CPU).
- Interrupt Controller,
Timer, and Watchdog control.
- Embedded SRAM memory used:
- Shared memory for
inter-processor communication: 64KB.
- Slave processor
(channel DSP tasks) base memory: 192KB.
- Master processor
(navigation, interfacing and service routines):
- Base
memory: 128KB.
- Battery
backup memory: 64KB.
- Video
memory: 64KB (dual-port synchronous
memory).
- 32/16-width external SRAM,
ROM and FLASH memory interface.
- Three basic modes of
operation
- Maximum resolution.
External video DRAM and LCD panel are used.
Resolution up to 1024x1024. Automatic DRAM
regeneration cycles.
- Only on-chip video
memory and video adapter are used, low-cost LCD
panel can be used.
Resolution up to 256x256.
- If video adapter is
not used, the on-chip adapter memory can be used
as an ordinary memory for the Master processor.
Read/Write interface with external video DRAM can
be used to connect additional DRAM of up to 16MB
to the processor core.
- Internal dual-port video
memory of 64KB size, 1KB color-lookup table, that gives
up to 512x256 resolution with 255 colors.
- Hardware cursor (64x64
pixels).
- Separated power supply.
- Alarms for system
"wakeup" from power-down mode or to generate
interrupt, external output.
- One-second data read and
alarm accuracy.
- Can be configured as either
transmitting or receiving channels.
- 32-bit hardware CRC
generation/check.
- Baud rate discriminator.
- Flexible DSS code generator
(see Navigation channels).
- Baud rates up to 128
Kbit/s.
- Baud rates from 300 bit/s
up to 460.8 Kbit/s.
- 32-bytes receive/transmit
FIFO with error flags.
- Automatic software/hardware
flow control.
- Independent infrared
outputs.
- Supported modes:
- Centronics
- Reverse Byte
- ECP (extended
capabilities port) with run-length
encoding/decoding
- EPP (enhanced
parallel port)
- More then 1 Mbytes/s
transfer rate in ECP and EPP modes.
- 64-bytes FIFO.
- Hardware handshaking
protocol implementation.
- Support for peripheral-side
operation.
- Composed of 16-bits in/out
port that can be used independently if a keyboard is not
needed.
- Minimized external
components set due to tristate outputs/pull-up resistors
-- needs only keyboard matrix.
- Two base configurations
available:
- 8 by 8 matrix gives
64 keys keyboard.
- Simpler controlled
16-bit input port gives 16-keys keyboard.
- Two sets of PLL dividers
and detectors for RF extension.
- Synchronous serial
peripheral interface (SPI) with four chips selects.
- Sound module.
- General purpose I/O port.
- 11-bit interface for LCD
controllers of any kind, except those that need CPU
provided regeneration capability.
- IDE interface.